As the speed of digital communication networks increases and data bandwidths become wider current serial CRC calculation methods and circuits are increasing gating transmission speed because of the time required to generate the CRC or are consuming ever increasing amounts of silicon real estate and power as gate counts increase. Even increasing gate counts not only impacts the physical layout in terms of wireability, but also increases the power consumption of the CRC circuit. Additionally, as data size decreases, the resultant large increase in the size of the CRC increases because of the poor resolution of parallel CRC circuits. Therefore, an improved CRC generation/checking methodology and circuit design is required for high speed, high resolution, and high bandwidth digital communication applications.